In many electronic devices and applications, high voltages may be found in high demand. For example, for a flash memory, a high voltage can be used to execute operations such as read, write and erase flash memory cells. This high voltage level can be typically generated inside an integrated circuit by using a high voltage generator and routed to appropriate destination points inside the chip. This routing can be done by using a switch inside the chip, and this switch used for routing the high voltage inside the chip to appropriate destination points is called a high voltage switch (HVS).
A high voltage generally means a voltage level higher than a device's power supply level. As explained above, a high voltage can be useful and sometime necessary for many electronic devices nowadays. Since a high voltage generally has a voltage level higher than that of the device's power supply, usually the high voltage is generated and managed inside the chip. For example, a high voltage generator can be embedded on a chip. This can optimize the high voltage generation as well as simplify the design of the circuit board on which the integrated circuit is to be employed. To this purpose, a charge-pump circuit or a voltage doubler circuit can be used. There can be other circuits used, but all of individual elements are not explained here because one of ordinary skill in the art would understand and know how to implement a state-of-art high voltage generator.
Once a high voltage is generated, it usually needs to be routed to a specific destination point inside the chip, such as a specific block or a specific line, in order to perform a given operation. For example, a high voltage level of around ˜18 v may be needed for a flash memory to perform program-operation, and this voltage needs to be delivered to a specific flash memory cell in order to program such cell. This routing of a high voltage inside the chip is typically managed by a high voltage switch inside the circuit. There are several state-of-art analog high voltage switch architectures that have been used or employed in most of state-of-art electronic integrated devices.
FIGS. 1a and 1b show examples of two different types of state-of-art high voltage switch configurations. FIG. 2 shows an example of a state-of-art level shifter circuit schematic, which may be employed in the examples shown in FIGS. 1a and 1b. 
FIG. 1a shows an example of a p-mos switch. This switch can be used to connect the high voltage line, SUPPLY_HV to the high voltage output line, OUT_HV. Alternatively, this switch can leave the high voltage output line, OUT_HV, floating so as to allow another switch to pass a different voltage level to high voltage output line OUT_HV. Block LEVEL SHIFTER represents a level shifter circuit. This level shifter can be used to drive the gate of the p-mos switch transistor, MP. The gate of MP is connected to output node of the level shifter, OUT_INT_HV. When the output of the level shifter is 0, p-mos switch transistor MP is turned on. Then, the switch can connect high voltage line SUPPLY_HV to high voltage output line OUT_HV. Alternatively, when the output of the level shifter is high (e.g., at SUPPLY_HV), p-mos switch transistor MP is turned off. Then, the switch does not connect high voltage line SUPPLY_HV to high voltage output line OUT_HV. Instead, high voltage output line OUT_HV is left floating. A bulk of p-mos switch transistors MP may be connected to the highest voltage available in the switch (not shown in the figure for simplicity).
FIG. 1b shows an example of n-mos switch. This switch can also be used to connect the high voltage line, SUPPLY_HV to the high voltage output line, OUT_HV. Alternatively, this switch can leave the high voltage output line, OUT_HV, floating so as to allow another switch to pass a different voltage level to high voltage output line OUT_HV. Block LEVEL SHIFTER represents a level shifter circuit. This level shifter can be used to drive the gate of the n-mos switch transistor, MN. The gate of MN is connected to output node of the level shifter, OUT_INT_HV. When the output of the level shifter is high (e.g., at SUPPLY_HV), n-mos switch transistor MN is turned on. Then, the switch can connect high voltage line SUPPLY_HV to high voltage output line OUT_HV. Alternatively, when the output of the level shifter is 0, n-mos switch transistor MN is turned off. Then, the switch does not connect high voltage line SUPPLY_HV to high voltage output line OUT_HV. Instead, high voltage output line OUT_HV is left floating. A bulk of n-mos switch transistors MN are connected to ground, which is not shown for simplicity.
In the state-of-art n-mos switch configurations, such as the one shown in FIG. 1b, the high voltage level supplied needs to be higher than the desired voltage level to be outputted. That is, when the high voltage supplied from SUPPLY_HV passes the n-mos switch transistor to reach high voltage output line OUT_HV, it suffers a voltage drop. That voltage drop can be attributed to the threshold voltage of the n-mos switch transistor. Therefore, if the desired high voltage output level to be detected at OUT_HV is, for example, V1, the voltage level supplied at SUPPLY_HV needs to be at least V1+Vth, when Vth represents the threshold voltage of the n-mos. However, sometimes such high voltage level is not available inside the chip. For example, it may not be within the voltage range that can be generated by the high voltage generator inside the chip. Therefore, the requirement that the high voltage supply level be greater than the desired high voltage output level has been conceived as one of important disadvantages associated with the state-of-art n-mos high voltage switch configurations.
On the other hand, the state-of-art p-mos switch configurations can have several drawbacks as well. One of the main drawbacks can be attributed to their inherent limitation in technology. That is, some p-mos transistors cannot sustain a certain voltage difference higher than the maximum set by the technology, between their drain/source and bulk terminal.
FIG. 3 shows an example of a cross section of a typical p-mos high voltage transistor. The voltage difference between p+ and high voltage n-well HV_NWELL may be limited in some technologies, so as not to exceed a maximum voltage level permitted/allowed by the technology (e.g., transistor specification), Vmax. If the voltage difference between p+ and HV_NWELL exceeds Vmax, then the transistor may suffer a junction breakdown and may not operate properly. Accordingly, if the supply high voltage level greater than Vmax is passed to the p-mos switch, the switch may break down and not operate properly. This can be an inherent limitation to the maximum voltage level that can be supplied to the switch, therefore to the device. Accordingly, the p-mos switch may not work well in the case when the device needs a high voltage output level greater than the maximum allowed by the technology associated with the p-mos.
To mitigate the problem associated with the p-mos transistors identified above, some have employed a local boosting circuit using n-mos transistors.
FIG. 4 shows an example of state-of-art switch configuration with a local boosting circuit.
FIG. 5 shows an example of simplified circuit schematic for a local boosting circuit. When enable signal EN_B is 0, the circuit is enabled. When the circuit is enabled, output line OUT_INT_HV is pre-charged to the voltage level substantially equal to “VDD−Vth(MN1).” Then, MN2 switch is turned on, which allows node B to pre-charge to the voltage level substantially equal to “VDD−Vth(MN1)−Vth(MN2).” During the first falling-edge of signal CLK, node B is boosted up through capacitor C2. Ideally, node B may be boosted up to the voltage level substantially equal to “2VDD−Vth(MN1)−Vth(MN2).” Then, diode D1 can become forward biased, and output line OUT_INT_HV can charge up to the ideal voltage level substantially equal to “2VDD−Vth(MN1)−Vth(MN2)−Vth(D1).” During the subsequent rising-edge of signal CLK, output line OUT_INT_HV is boosted up through capacitor C1. Ideally, OUT_INT_HV may be boosted up to the voltage level substantially equal to “3VDD−Vth(MN1)−Vth(MN2)−Vth(D1).” Then, node B can ideally charge up as well to the voltage level substantially equal to “3VDD−Vth (MN1)−2Vth(MN2)−Vth(D1).” Ideally, this loop may repeat until node B reaches the voltage level substantially equal to “SUPPLY_HV.” This may allow output line OUT_INT_HV to reach an ideal voltage level that is substantially equal to VSUPPLY_HV+2VDD−Vth(D1).
If that voltage value substantially equal to “VSUPPLY_HV+2VDD−Vth(D1),” is greater than VSUPPLY_HV reduced by the threshold voltage with body effect of n-mos switch transistor, then the n-mos switch configuration in FIG. 4 is able to fully pass SUPPLY_HV voltage value to output node OUT_HV.
Diodes D2 and D3 of FIG. 5 are used to clamp the voltage value of node OUT_INT_HV to the level substantially equal to “VSUPPLY_HV+2Vth(D2,3) to reduce breakdown risks.
Further, the circuit in FIG. 5 may be switched off by setting signal EN_B to logic 1 and simultaneously switching off signal CLK. When the circuit is switch off, node OUT_INT_HV may be discharged to ground through MN1 and INV1.
However, there can still be a drawback with this type of state-of-art switch architecture employing a local booster circuit. That is, these circuits such as the one shown in FIG. 5 may incur a large DC current consumption due to their continuous boosting operations. This DC current consumption problem may be worsened by the intrinsic low efficiencies of the employed boosting schemes.